1. Field of the Invention
This invention relates to semiconductor processing and, in particular, to processing of III-V based semiconductor materials.
2. Art Background
A variety of devices based on III-V semiconductor materials, i.e., III-V binaries, ternaries, pseudoternaries, and pseudoquaternaries containing at least one group III and at least one group V entity, has been produced. For example, both discrete components such as gallium arsenide field effect transistors (FETs) and also gallium arsenide integrated circuits have been made. These devices exhibit desirable properties such as relatively high-speed operation due to the advantageous properties of III-V based semiconductor materials, e.g., the high resistivity or high-carrier mobility of suitably doped III-V based semiconductor materials.
Despite the advantages offered by devices based on III-V semiconductor materials, certain aspects of these devices, although acceptable, could still advantageously be improved. For example, the active region of GaAs FETs is generally built upon a semi-insulating buffer layer. This buffer layer interposed between the device active region and the substrate is used to avoid the undesirable effects such as degraded mobility of carriers in proximity to an active layer/substrate interface. (See, for example, T. Nozaki et al, Institute of Physics Conference Series, 24, 46 (1975).) This buffer layer is usually formed by epitaxially depositing a chrome-doped GaAs material onto the GaAs substrate. By employing chrome compensation for the background impurity-induced carrier concentration, the resulting doped GaAs has a suitably high resistivity, e.g., above approximately 10.sup.6 ohm-cm as compared to about 1 ohm-cm for nominally undoped GaAs material grown by conventional chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) deposition techniques.
Although chrome-doped, semi-insulating layers are presently being employed with great success in device structures, the concentration of the chrome dopant is not precisely controllable. Thus, from one deposition run to another, the background carrier concentration will vary in an unpredictable manner. Compensation for this background is done for an average background level. The variation between the average background level and the actual level, together with the variation between desired compensation level and the level actually produced, leads to under or overcompensation. In addition, the chrome dopant has a tendency, especially in the case of overcompensation, to diffuse into the device active region. This diffusion, although in no way catastrophic, introduces difficulties in maintaining the discrete active layer/buffer layer interface which is required for producing the most efficient device operation. Nevertheless, an acceptable alternative to chrome doping which produces an appropriate semi-insulating region with appropriate resistivity has not been developed.
Dopants other than chrome are also introduced into III-V based semiconductor material to provide a relatively high majority carrier concentration. Such III-V based semiconductor materials made by presently employed techniques involving CVD are quite acceptable. (Mobilities on the order of 10.sup.5 cm.sup.2 /Vs and higher are achieved.) These conductive materials are used, for example, to form the active region of various devices. When used in these applications, limitations on thickness as well as dopant control present in CVD methods become significant. It is typically difficult to control CVD layers to better than .+-.0.1 .mu.m from one deposition run to another. Additionally, the thickness across a deposited layer is somewhat nonuniform, e.g., thickness variations greater than .+-.10 percent. These variations, across a layer and from one layer to another, prevent the deposition of thin layers, i.e., layers less than about 0.1 .mu.m thick. Since thin layers are not available, devices such as selectively doped heterostructure transistors (SDHT) and normally off III-V based FETs that involve thin layers of precisely controlled thicknesses are not producible by CVD. (See T. Mimura, S. Hiyamizu, T. Fujii and K. Nanbu, Japanese Journal of Applied Physics, 19, L225 (1980).) The inability to produce normally off III-V FETs, in turn, severely limits the usefulness of III-V integrated devices.
In contrast, MBE has been used to produce relatively uniform layers of III-V based semiconductor material as thin as 100 .ANG.. However, as previously discussed, III-V based semiconductor devices rely on the relatively high-carrier mobilities of III-V based semiconductor material to offer the possibility of enhanced properties such as low field device operation and relatively high-speed operation. (Parasitic capacitance is inevitably present in a device. Typical operating fields in conjunction with this capacitance introduce significant time delays, while relatively low fields do not.) Despite its advantageous characteristics relating to thickness control, MBE procedures have produced mobilities in doped layers that are somewhat worse than those obtained in doped layers produced by CVD. Thus, presently available techniques, although quite acceptable, do limit the properties of III-V based devices.